n0211 sy/o2809 sy / d1008 ms 20081201-s00005 no.a1382-1/6 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 LV8406T overview LV8406T is a 2-channel forward/reverse motor driver ic using d-mos fet for output stage. as mos circuit is used, it supports the pwm input. its features are that the on resistance (0.75 typ) and current dissipation are low. it also provides protection functions such as heat protection circuit and reduced voltage detection and is optimal for the motors that need high-current. functions ? 2-channel forward/reverse motor driver. ? built-in low voltage reset and thermal shutdown circuit. ? low power consumption. ? four mode function forward/reverse, brake, stop. ? low-on resistance 0.75 . ? built-in charge pump. specifications absolute maximum ratings at ta = 25 c, sgnd = pgnd = 0v parameter symbol conditions ratings unit power supply voltage (for load) vm max vm1, vm2 -0.5 to 16.0 v power supply voltage (for control) v cc max -0.5 to 6.0 v output current i o max 1.4 a output peak current i o peak t 10ms 2.5 a input voltage v in max -0.5 to v cc +0.5 v allowable power dissipation pd max mounted on a specified board* 3.1 w operating temperature topr -30 to +85 c storage temperature tstg -55 to +150 c * specified board : 90mm 90mm 1.6mm, glass epoxy 2-layer board (2s0p). caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of th e ic may be degraded. please contact us for the further detai ls. bi-cmos ic 2ch forward/reverse motor driver orderin g numbe r : ena1382b stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV8406T no.a1382-2/6 allowable operating conditions at ta = 25 c, sgnd = pgnd = 0v parameter symbol conditions ratings unit power supply voltage (vm pin) vm 1.5 to 15.0 v power supply voltage (v cc pin) v cc 2.8 to 5.5 v input signal voltage v in 0 to v cc v input signal frequency f max 200 khz electrical characteristics ta = 25 c, v cc = 3.0v, vm = vs = 6.0v, sgnd = pgnd = 0v, unless otherwise specified. ratings parameter symbol conditions remarks min typ max unit standby load current drain imo en = 0v 1 1.0 a standby control current drain ico en = in1 = in2 = in3 = in4 = 0v 2 1.0 a standby load current drain2 imo2 v cc = 0v, vm = vs = 6v 1.0 a operating control current drain ic1 en = 3v, with no load 3 0.85 1.2 ma high-level input voltage v ih 2.7 v cc 5.5v 0.6 v cc v cc v low-level input voltage v il 2.7 v cc 5.5v 0 0.2 v cc v high-level input current (en1, en2, in1, in2, in3, in4) i ih 1 v in = 3v 4 15 25 a low-level input current (en1, en2, in1, in2, in3, in4) i il 1 v in = 0v 4 -1.0 a pull-down resistance value rdn en1, en2, in1, in2, in3, in4 100 200 400 k charge pump voltage vg v cc + vs 8.5 9.0 9.5 v output on resistance 1 ron1 sum of top and bottom sides on resistance. 5 0.75 1.2 output on resistance 2 ron2 sum of top and bottom sides on resistance. v cc = 2.8v 5 1.0 1.5 low-voltage detection voltage vcs v cc pin voltage is monitored 6 2.15 2.30 2.45 v thermal shutdown temperature tth design guarantee value * 7 150 180 210 c turn-on time tplh 8 0.2 0.4 s output block turn-off time tphl 8 0.2 0.4 s * : design guarantee value and no measurement is preformed. remarks 1. current consumption when output at the vm pin is off. 2. current consumption when the v cc pin when in standby mode. 3. current consumption at the v cc pin when en is 3v (standby mode). 4. pins en1, 2, in1, 2, 3, and 4 are all pulled down. 5. sum of upper and lower saturation voltages of out pin divided by the current. 6. all power transistors are turned off if a low v cc condition is detected. 7. all output transistors are turned off if the thermal protection circuit is activated. they are turned on again as the temperature goes down. 8. rising time from 10 to 90% and falling time from 90 to 10% are specified.
LV8406T no.a1382-3/6 package dimensions unit : mm (typ) 3279 6.4 0.65 4.4 (0.33) (1.0) 6.5 0.5 0.15 1 10 20 11 0.22 0.08 1.2max side view bottom view exposed die-pad top view sanyo : tssop20j(225mil) substrate specifications size : 90mm 90mm 1.6mm (2-layer substrate [2s0p]) material : glass epoxy copper wiring density : l1 = 95% / l2 = 95% l1 : copper wiring pattern diagram l2 : copper wiring pattern diagram cautions 1) the data for the case with the exposed die-pad substrate mounted shows the values when 90% or more of the exposed die-pad is wet. 2) for the set design, employ the derating design with sufficient margin. stresses to be derated include the voltage, current, junctio n temperature, power loss, and mechanical stresses such as vibration, impact, and tension. accordingly, the design must ensure these stresses to be as low or small as possible. the guideline for ordinary derating is shown below : (1)maximum value 80% or less for the voltage rating (2)maximum value 80% or less for the current rating (3)maximum value 80% or less for the temperature rating 3) after the set design, be sure to verify the design with the actual product. confirm the solder joint state and verify also the re liability of solder joint for the exposed die-pad, etc. any void or deterioration, if observed in the solder jo int of these parts, causes deteriorated thermal conduction, possibly resulting in thermal destruction of ic. -30 0 20406080100 0 4,0 3.0 2.0 1.0 pd max -- ta 3.1 -20 1.61 85 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board: 90 90 1.6mm 3 glass epoxy 2-layer (2s0p) with components mounted on the exposed die-pad board.
LV8406T no.a1382-4/6 pin assignment vg vm1 1 2 3 4 5 7 8 9 out1 out2 pgnd out3 out4 vm2 20 19 18 17 16 15 14 13 v cc in2 in1 sgnd c1l c1h top view LV8406T 6 pgnd 10 in4 en2 12 in3 11 en1 vs block diagram v cc in2 in1 en2 en1 in4 in3 c1h c1l vg vs out1 vm1 out2 out3 vm2 out4 pgnd startup control block thermal protection circuit reduced- voltage protection circuit motor control logic charge pump v cc +vs * connect a kickback absorption capacitor as near as possibl e to the ic. coil kickback may cause increase in vm line voltage, and a voltage exceeding the maximum rating may be applied momentarily to the ic, which results in deterioration or damage of the ic * the pin vs is a terminal that supplies a s ource power supply of the charge pump circuit. the charge pump voltage, vg = vs + v cc is generated. apply the high voltage of vm1 or vm2.
LV8406T no.a1382-5/6 truth table en1 (en2) in1 (in3) in2 (in4) out1 (out3) out2 (out4) charge pump mode h h l l brake h l h l forward l h l h reverse h l l z z on standby l - - z z off all function stop - : denotes a don't care value. z : high-impedance ? in standby mode, consumption current serves as zero.. * all power transistors turn off and the motor stops driving when the ic is detected in low voltage or thermal protection mode. pin functions pin no. pin name description equivalent circuit 20 1 17 c1h vg vs step-up capacitor connection pin. charge pump source voltage supply pin. vs c1h vg 19 c1l step-up capacitor connection pin. c1l v cc internal osc 16 12 15 14 11 10 en1 en2 in1 in2 in3 in4 logic enable pin. (pull-down resistor incorporated) driver output switching. v cc 200k 3 4 7 8 out1 out2 out3 out4 driver output. out out vm pgnd 2 9 vm1 vm2 motor block power supply. 13 v cc logic block power supply. 18 sgnd control block ground. 5 6 pgnd pgnd driver block ground.
LV8406T ps no.a1382-6/6 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
|
